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我是一个芯片验证工程师，在日常工作中，python是我最重要的scripting language。现在我还用python的[http://wiki.python.org/moin/MyHDL MyHDL] package来搭建testbench, it works well。我的兴趣范围还包括[wiki:ChunLinZhang/SystemC SystemC], [wiki:ChunLinZhang/Specman Specman], [wiki:ChunLinZhang/SystemVerilog SystemVerilog], testbench automation，coverage driven verification等，希望能和IC design领域的同行多多交流。

Verification vs. Test

• Verification Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function

• Test A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

• [http://www.eng.auburn.edu/~vagrawal/ website about test]

Equivalence Check / STA

• FPGA approach

SynplifyPro -> Conformal (lec) -> ISE Timing Analyzer (trce)BR set verification mode on in Synplify to generate the .vif file, use vif2conformal to translate the vif file the a format that recognizible by conformal. The inputs of trce is .ncd and .pcf files

• ASIC approach

Design Compiler -> Formality -> PrimeTime

技术类

Include(ChunLinZhang/bookmark)

• [wiki:ChunLinZhang/projects 我的项目]

   1 from myhdl import *

{zh} [email protected]

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