我的项目

Contents

  1. Current Project
    1. Overview
    2. Verification Strategy
      1. constraint random
      2. coverage driven
        1. code coverage
        2. functional coverage
      3. assertion based
      4. Technologies and Tools
    3. 验证环境
      1. ASIC simulation environment
      2. FPGA simulation environment
      3. FPGA prototyping board
    4. Coverage Metrics
    5. Regression
    6. 软硬件协同验证(Co-Verification)
      1. FPGA code base simulation
    7. Project Management
    8. env user guide
      1. FPGA Prototyping Env. Setup
      2. IPPorter的bringup
      3. FPGA Testing
看看我都做了些什么, My goal is to be an expert consultant!!!

Current Project

Overview

建立一个嵌入式控制器芯片(SoC)的功能验证环境。这个芯片有embedded java processor，采用wishbone总线结构。

Verification Strategy

Productized Methodologies, Reuse, Block to System-Level Verification, Coverage

constraint random

There is no existing constraint solver in python, so each random constraint had to be written explicitly in test env.

coverage driven

code coverage

functional coverage

利用PSL中的cover来统计control based functional coverage

assertion based

用PSL作为assertion language。Simulation-Based ABV and FA are complementary technologies. Assertions written for use in FA can be also checked in simulation. Conversely, assertions written for use in simulation-based ABV can be used in FA. Other tools, such as emulation, may also be able to check the same assertions. During simulation, assertions act as monitors that check for expected behavior. The main issue with simulation-based assertion checking is that it requires test vectors, and is therefore, limited by the amount and quality of these test vectors.

Technologies and Tools

验证环境

ASIC simulation environment

verif.tdraw

FPGA simulation environment

This environment is developed to help locating bugs when something weird found in FPGA prototyping board. It has almost the same architecture as ASIC simulation environment, but with different tb_top and different internal memory structure.

FPGA prototyping board

Coverage Metrics

Code coverage analysis is mandatory in this project. Block/Path/Expression coverage are analysed. FSM coverage data is not analysed in this stage.

Functional Coverage is a relatively new concept in this project, so this coverage data collection and analysis is optional for each IP.

Regression

A seperate script written in python is used for regression. This script has the ability to run all of the test cases in a list file, and then generate a report summary file. 

s25_regress.py -f <filename>

s25_regress.py -v -f <filename>

s25_regress.py --fpgaboard -f <filename>

软硬件协同验证(Co-Verification)

很想拥有mentor的seemless，可是我没有。只好自力更生，自己开发一个co-verification的环境出来。
mytest.tdraw
上图中terminal是一个用python开发出来的Command Line Interface(CLI)。它可以将处理器的程序编译成为二进制代码后通过Socket Inter Process Communication传送给仿真环境，仿真环境将接收来的数据作为UART的输入数据，芯片内置的firmware将通过UART接收来的程序数据放置到预先设定的RAM空间，然后再跳转到该空间开始执行相应的程序。当FPGA prototyping和它连接时，则需要将连接的方式改为PC的串口。

这样一个系统的优点是在芯片硬件开发的同时，driver/diagnostic/application软件可以并行开发，而不是必须等待FPGA board ready or real chip back，another advantage is that we can have almost unlimited copies of this development environment in simulation instead of limited copies of FPGA board which sometimes restricted us from putting more human resources into the software development when it becomes the critical path of the whole project.

FPGA code base simulation

In one terminal 

cd sandbox/s25/SIM/verif/sim
s25_run.py -c -w --fpga test_cover -s 1 -l

Here, -c means compile the code base, --fpga means use the fpga code base, -w means waveform will be dumped, -s 1 means use 1 as the random seed, -l means simulation log file will not be recorded. test_cover is just a test case name, it has no special meaning here, as the firmware is always hard-wired in sprom16kx32_init.v in sandbox/s25/SIM/fpga/rtl

In another terminal 

cd sandbox/s25/SIM/verif/sim
s25_cover.py

Inside the terminal of s25_cover.py, the command list should like below: 

setup asic
read 0xc2100
write 0xc2100 789
run 10000
exit

ToDO:

Project Management

cvs is adapted for revision control，Rational ClearQuest is adapted as issue/bug tracking tool

env user guide

FPGA Prototyping Env. Setup

The power supply of the target board is +5v, however, due to the bad quality of the DC regulator, the switch should pointer +12v, otherwise, the target board will not work properly, the LED display in the target board is dim.

IPPorter的bringup

cd /etc/rc.d/init.d
./ipporterd start

After this, you should be able to see s2c information from the LCD of IPPorter. If not, something wrong, you should disconnect the power supply and USB port, let the capacitor discharge for several minutes, then try again, normally you can see s2c information now. 

s2c &

cd /etc/rc.d/init.d
./ipporterd stop

For Prototype Navigator v Beta1.0.14, things need to be modified manually listed below:

For Prototype Navigator v Beta 1.0.15, 

s25_s2c.py

s25_s2c.py --pack --name <filename> --path <project file folder>

s25_s2c.py --download <filename>

FPGA Testing

You should run a test at sandbox/s25/SIM/verif/sim, command to run a single test is 

s25_run.py --fpgaboard <testcasename> --seed <random seed>

testcase is stored at sandbox/s25/SIM/verif/tests, generally, the name should start with fpga_, in each test case, testing program and the expected return value through uart should be specified.

ChunLinZhang/projects (last edited 2009-12-25 07:14:15 by localhost)