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| == Verification vs. Test == * ''Verification'' Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function * ''Test'' A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect. * [http://www.eng.auburn.edu/~vagrawal/ website about test] |
个人主页 TableOfContents 纪录一些自己经常访问的网站
个人兴趣
我是一个芯片验证工程师，在日常工作中，python是我最重要的scripting language。现在我还用python的MyHDL package来搭建testbench, it works well。我的兴趣范围还包括SystemC，SystemVerilog，testbench automation，coverage driven verification等，希望能和IC design领域的同行多多交流。
Verification vs. Test
Verification Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function
Test A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
[http://www.eng.auburn.edu/~vagrawal/ website about test]
技术类
[http://www.python.org python官方网站]
[http://www.systemc.org OSCI官方网站]
[http://www.51eda.com/bbs 51EDA]
[http://www.synplicity.com synplicity]
[http://www.xilinx.com xilinx]
[http://www.xdush.com/bbs 西电上海校友会]
[http://info.cmbchina.com 招商银行]
[http://www.shmc.com.cn 上海移动]
[http://www.okng.com 数字卡]
[http://www.shfft.com 付费通]
[https://www.95559.sh.cn:446/pubbank/private/privatelogin.jsp 交通银行]
[http://bt.btchina.net/?categoryid=-1 BT Hot List]
[http://192.168.8.7/vqwiki/jsp/index.jsp wiki in java]
[http://192.168.8.7:10010/cqweb/logon/default.asp ClearQuest]
[wiki:ChunLinZhang/bookmark 我经常访问的地方]
[wiki:ChunLinZhang/projects 我的项目]
1 from myhdl import *
{zh} [email protected] 