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'''个人主页'''
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'''
纪录一些自己经常访问的网站'''		 ''' Welcome to my verification world! Hope the resource here is helpful for your ASIC verification projects. '''

= scripting =
''' python is the most important scripting language for me. '''
 * wrap up the verification environment
 * text parsing, especially for simulation log file post processing
 * parsing/generation of testcases, memory image, etc
 * simulation environment command line interface for co-verification environment
 * regression report generation, an excel spreadsheet file will be generated based on all testcase files and simulaton results
 * setup the environment variables for all EDA tools, end user need not to care about how to setup the tools, where to checkout licenses, etc
''' I used to write Tcl script for a long time '''
 * to remote-control electronic instruments, such as ATM signal generator/analyzer from ADTECH
 * adopted by most of EDA tools as the scriping language when running in batch mode
''' no need to say, shell is also a very important scripting language ''' [[BR]]
 ksh is the first shell I used, then I moved to bash, however, csh/tcsh is widely used in EDA industry, I don't want to speak a dialect. :( [[BR]]
''' other useful collections from the web '''
 * [http://www.edaboard.com/viewtopic.php?t=76718&sid=d1a842f8bb135206c95564ed51f25332 Using perl or cshell script to perform daily task]
 * Tcl/Tk is a glue language, a good artical [http://wiki.tcl.tk/11834 Tcl over Python]
 * [http://www.equi4.com/minotaur/minotaur.html Minotaur] for Perl, Python and Tcl, if you need to mix these scripting languages in one file, try this. The bad thing is that nobody maintain it anymore and no document about the actual usage.
 * [http://aspn.activestate.com/ASPN/CodeDoc/Inline-Tcl/Tcl.html Inline Tcl] best, I think, anybody can tell me is there a corespond in python?
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我是一个芯片验证工程师，在日常工作中，python是我最重要的scripting language。现在我还用python的MyHDL package来搭建testbench, it works well。我的兴趣范围还包括SystemC，SystemVerilog，testbench automation，coverage driven verification等，希望能和IC design领域的同行多多交流。 现在我还用python的[http://wiki.python.org/moin/MyHDL MyHDL] package来搭建testbench, it works well。我的兴趣范围还包括[wiki:Self:ChunLinZhang/SystemC SystemC], [wiki:Self:ChunLinZhang/Specman Specman], [wiki:Self:ChunLinZhang/SystemVerilog SystemVerilog], [wiki:Self:ChunLinZhang/PSL PSL], testbench automation，coverage driven verification等，希望能和IC design领域的同行多多交流。
== fpga prototyping ==
 * [http://www.hardi.com HARDI HAPS]
 * [http://www.s2cinc.com S2C IPPorter]
 * [http://www.dynalith.com iProve]
 * [http://www.eve-team.com/index.html eve]
== Verification vs. Test ==
 * ''Verification'' Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function
 * ''Test'' A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.
 * [http://www.eng.auburn.edu/~vagrawal/ website about test]
== Equivalence Check / STA ==
 * FPGA approach
{{{SynplifyPro -> Conformal (lec) -> ISE Timing Analyzer (trce)}}}[[BR]]
set verification mode on in Synplify to generate the .vif file, use vif2conformal to translate the vif file the a format that recognizible by conformal. The inputs of ''trce'' is .ncd and .pcf files, before we can use these files generated by Synplify with lec, we had to change all these file format using dos2unix, and add -define FPGA to the .vtc file. I can't understand why Synplify failed to add this switch to the .vtc file. [[BR]][[BR]]
Set the verification mode on will greatly slow the the synthesis speed. The whole lec process will take about 1 and a half hours to complete.
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= 现在的项目 =
== 项目概述 ==
建立一个嵌入式控制器芯片(SoC)的功能验证环境。这个芯片有embedded java processor，采用wishbone总线结构。
== 验证策略 ==
=== constraint random ===
=== coverage driven ===
==== code coverage ====
==== functional coverage ====
=== assertion based ===
用PSL作为assertion language，并且利用其中的cover来统计control based functional coverage。
=== Technologies and Tools ===
 * Simulator采用Cadence的IUS54
 * Debugger采用Novas的Debussy 5.4v7。
 * Code Coverage analysis采用Cadence的Incisive Coverage Tool, 其实说白了就是hdlscore。
== 验证环境 ==
drawing:mytest
== Coverage Metrics ==
== Regression ==
== 项目管理 ==
== env user guide ==		  * ASIC approach
{{{Design Compiler -> Formality -> PrimeTime}}}
 * [http://www.edaboard.com/viewtopic.php?t=81857&sid=d1a842f8bb135206c95564ed51f25332 What is Equivalence Checking?]

== documentation ==
 * latex
 * wiki, I use moinmoin as the engine, and sometimes, use python package [https://moin.conectiva.com.br/EditMoin EditMoin] to edit the moin pages with vim. It is a pure python implementation, and I made the following modification to make it works for me :)
{{{#!python
# original code commented out
# self.datestamp = self._get_data(DATESTAMPRE, "datestamp")
self.datestamp = ''
}}}
== processing excel with python ==
=== read ===
[http://www.lexicon.net/sjmachin/xlrd.htm xlrd]从python.cn上看到的介绍，自己没有试过。
=== write ===
[http://sourceforge.net/projects/pyxlwriter/ xlwriter] I have ever used this package to generate the summary verification report, quite good to do the same kind of work like report auto-generation. It is also platform independent. The bad side is not very easy to control the format. Some sample code:
{{{#!python
import pyXLWriter as xl
def report_autogen(filename):
    wbk = xl.Writer(filename)
    sumsheet = wbk.add_worksheet('Summary')
    wbk.close()
    return 0
}}}
== xml and python ==
XML-RPC for distributed computation, functions will be defined in the server side, client side can call these functions via http POST with xml as the embeded content.
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 * [http://www.python.org python官方网站]
 * [http://www.systemc.org OSCI官方网站]
 * [http://www.51eda.com/bbs 51EDA]
 * [http://shera-ccserver/vqwiki/jsp/index.jsp wiki in java]
 * [wiki:Self:ChunLinZhang/bookmark 我经常访问的地方]		 [[Include(ChunLinZhang/bookmark)]]
 * [wiki:Self:ChunLinZhang/projects 我的项目]
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#!python
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= QA =
 * [http://www.qaforums.com/ultimatebb.php?ubb=get_topic;f=39;t=000528 Procedure Templates]
= 精品电子书 =

 * [http://www.amazon.com/exec/obidos/tg/detail/-/1402078757/104-1722879-4423959?v=glance Professional Verification] -- A Guide to Advanced Funcational Verication, by Paul Wilcox, Cadence Design Systems, Inc.
comment: This book is almost same as the IUS document UVM

TableOfContents Welcome to my verification world! Hope the resource here is helpful for your ASIC verification projects.

scripting

python is the most important scripting language for me.

  • wrap up the verification environment
  • text parsing, especially for simulation log file post processing
  • parsing/generation of testcases, memory image, etc
  • simulation environment command line interface for co-verification environment
  • regression report generation, an excel spreadsheet file will be generated based on all testcase files and simulaton results
  • setup the environment variables for all EDA tools, end user need not to care about how to setup the tools, where to checkout licenses, etc

I used to write Tcl script for a long time

  • to remote-control electronic instruments, such as ATM signal generator/analyzer from ADTECH
  • adopted by most of EDA tools as the scriping language when running in batch mode

no need to say, shell is also a very important scripting language BR

  • ksh is the first shell I used, then I moved to bash, however, csh/tcsh is widely used in EDA industry, I don't want to speak a dialect. :( BR

other useful collections from the web

个人兴趣

现在我还用python的[http://wiki.python.org/moin/MyHDL MyHDL] package来搭建testbench, it works well。我的兴趣范围还包括[wiki:ChunLinZhang/SystemC SystemC], [wiki:ChunLinZhang/Specman Specman], [wiki:ChunLinZhang/SystemVerilog SystemVerilog], [wiki:ChunLinZhang/PSL PSL], testbench automation，coverage driven verification等，希望能和IC design领域的同行多多交流。

fpga prototyping

Verification vs. Test

  • Verification Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function

  • Test A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

  • [http://www.eng.auburn.edu/~vagrawal/ website about test]

Equivalence Check / STA

  • FPGA approach

SynplifyPro -> Conformal (lec) -> ISE Timing Analyzer (trce)BR set verification mode on in Synplify to generate the .vif file, use vif2conformal to translate the vif file the a format that recognizible by conformal. The inputs of trce is .ncd and .pcf files, before we can use these files generated by Synplify with lec, we had to change all these file format using dos2unix, and add -define FPGA to the .vtc file. I can't understand why Synplify failed to add this switch to the .vtc file. BRBR Set the verification mode on will greatly slow the the synthesis speed. The whole lec process will take about 1 and a half hours to complete.

  • ASIC approach

Design Compiler -> Formality -> PrimeTime

documentation

  • latex

  • wiki, I use moinmoin as the engine, and sometimes, use python package [https://moin.conectiva.com.br/EditMoin EditMoin] to edit the moin pages with vim. It is a pure python implementation, and I made the following modification to make it works for me :) 

   1 # original code commented out
   2 # self.datestamp = self._get_data(DATESTAMPRE, "datestamp")
   3 self.datestamp = ''

processing excel with python

read

[http://www.lexicon.net/sjmachin/xlrd.htm xlrd]从python.cn上看到的介绍，自己没有试过。

write

[http://sourceforge.net/projects/pyxlwriter/ xlwriter] I have ever used this package to generate the summary verification report, quite good to do the same kind of work like report auto-generation. It is also platform independent. The bad side is not very easy to control the format. Some sample code: 

   1 import pyXLWriter as xl
   2 def report_autogen(filename):
   3     wbk = xl.Writer(filename)
   4     sumsheet = wbk.add_worksheet('Summary')
   5     wbk.close()
   6     return 0

xml and python

XML-RPC for distributed computation, functions will be defined in the server side, client side can call these functions via http POST with xml as the embeded content.

技术类

Include(ChunLinZhang/bookmark) 

   1 from myhdl import *

QA

精品电子书

comment: This book is almost same as the IUS document UVM

{zh} [email protected] :)

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Nicran (last edited 2009-12-25 07:09:28 by localhost)