我的项目 TableOfContents 看看我都做了些什么

现在的项目

项目概述

建立一个嵌入式控制器芯片(SoC)的功能验证环境。这个芯片有embedded java processor，采用wishbone总线结构。

验证策略

constraint random

There is no existing constraint solver in python, so each random constraint had to be written explicitly in test env.

coverage driven

code coverage

functional coverage

利用PSL中的cover来统计control based functional coverage

assertion based

用PSL作为assertion language。Simulation-Based ABV and FA are complementary technologies. Assertions written for use in FA can be also checked in simulation. Conversely, assertions written for use in simulation-based ABV can be used in FA. Other tools, such as emulation, may also be able to check the same assertions. During simulation, assertions act as monitors that check for expected behavior. The main issue with simulation-based assertion checking is that it requires test vectors, and is therefore, limited by the amount and quality of these test vectors.

Technologies and Tools

• Simulator采用Cadence的IUS54
• Debugger采用Novas的Debussy 5.4v7。
• Code Coverage analysis采用Cadence的Incisive Coverage Tool, 也就是hdlscore。
• Formal Verification -- Synopsys的Formality有人反映不是很稳定，前些日子看到Cadence推出了Incisive Formal Verifier，可惜的是，这个tool需要新的license feature Incisive_Formal_Verifier，并且还存在一些bug，所以只好暂时放弃。
• Emulation -- 这个项目里面采用了S2C公司的IPPorter，但是效果不是很好，姑且当作一个FPGA prototyping board来用吧！

• FPGA Synthesis 采用 Synplicity的SynplifyPro8.1，需要注意的是产生license时，机器的时间需要临时修改成04-11-16。

验证环境

drawing:verif

Coverage Metrics

Code coverage analysis is mandatory in this project. Block/Path/Expression coverage are analysed. FSM coverage data is not analysed in this stage.

Functional Coverage is a relatively new concept in this project, so this coverage data collection and analysis is optional for each IP.

Regression

A seperate script written in python is used for regression. This script has the ability to run all of the test cases in a list file, and then generate a report summary file.

软硬件协同验证(Co-Verification)

很想拥有mentor的seemless，可是我没有。只好自力更生，自己开发一个co-verification的环境出来。BR drawing:mytest BR 上图中terminal是一个用python开发出来的Command Line Interface(CLI)。它可以将处理器的程序编译成为二进制代码后通过Socket Inter Process Communication传送给仿真环境，仿真环境将接收来的数据作为UART的输入数据，芯片内置的firmware将通过UART接收来的程序数据放置到预先设定的RAM空间，然后再跳转到该空间开始执行相应的程序。当FPGA prototyping和它连接时，则需要将连接的方式改为PC的串口。BRBR 这样一个系统的优点是在芯片硬件开发的同时，driver/diagnostic/application软件可以并行开发，而不是必须等待FPGA board ready or real chip back，another advantage is that we can have almost unlimited copies of this development environment in simulation instead of limited copies of FPGA board which sometimes restricted us from putting more human resources into the software development when it becomes the critical path of the whole project.BRBR ToDO:

• change the read command to adjust the wait time according the baud rate, otherwise, some bogus error message will appear.

项目管理

cvs is adapted for revision control，Rational ClearQuest is adapted as issue/bug tracking tool

env user guide

IPPorter的bringup

• In root

cd /etc/rc.d/init.d
./ipporterd start

• In normal User

s2c &

Things need to be modified manually listed below:

• after Create Partition, you had to modify the pin name of global clock from PIO_O to PIO_CLK_O in fpga_bm.rpt in the folder of projDir/ace

• before place & route, you need to copy the information of rom location constraint in ncf file located at projDir/ace/apsout/F3/*.ncf

• if you need to use ILA and need to probe internal signals of the design, you had to remove the path information in projDir/ace/fpga_bm/*.cell
• for a new project, you can copy the pin location information before Assign IO Connectors
• before download the bin file to IPPorter, you should run the bat file in the genBin directory.