我的项目 TableOfContents 看看我都做了些什么

现在的项目

项目概述

建立一个嵌入式控制器芯片(SoC)的功能验证环境。这个芯片有embedded java processor，采用wishbone总线结构。

验证策略

constraint random

coverage driven

code coverage

functional coverage

利用PSL中的cover来统计control based functional coverage

assertion based

用PSL作为assertion language。Simulation-Based ABV and FA are complementary technologies. Assertions written for use in FA can be also checked in simulation. Conversely, assertions written for use in simulation-based ABV can be used in FA. Other tools, such as emulation, may also be able to check the same assertions.

Technologies and Tools

• Simulator采用Cadence的IUS54
• Debugger采用Novas的Debussy 5.4v7。
• Code Coverage analysis采用Cadence的Incisive Coverage Tool, 也就是hdlscore。
• Formal Verification -- Synopsys的Formality有人反映不是很稳定，前些日子看到Cadence推出了Incisive Formal Verifier，很感兴趣，现在正在尝试如何将这个tool apply到项目里面来。
• Emulation -- 这个项目里面采用了S2C公司的IPPorter，但是效果不是很好，姑且当作一个FPGA prototyping board来用吧！

验证环境

drawing:verif

Coverage Metrics

Code coverage analysis is mandatory in this project. Block/Path/Expression coverage are analysed. FSM coverage data is not analysed in this stage.

Functional Coverage is a relatively new concept in this project, so this coverage data collection and analysis is optional for each IP.

Regression

A seperate script written in python is used for regression. This script has the ability to run all of the test cases in a list file, and then generate a report summary file.

软硬件协同验证(Co-Verification)

很想拥有mentor的seemless，可是我没有。只好自力更生，自己开发一个co-verification的环境出来。 drawing:mytest

项目管理

cvs is adapted for revision control，Rational ClearQuest is adapted as issue/bug tracking tool

env user guide