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| == 技术类 == | = 现在的项目 = == 项目概述 == 建立一个嵌入式控制器芯片(SoC)的功能验证环境。这个芯片有embedded java processor，采用wishbone总线结构。 == 验证策略 == === constraint random === === coverage driven === ==== code coverage ==== ==== functional coverage ==== === assertion based === 用PSL作为assertion language，并且利用其中的cover来统计control based functional coverage。 === Technologies and Tools === * Simulator采用Cadence的IUS54 * Debugger采用Novas的Debussy 5.4v7。 * Code Coverage analysis采用Cadence的Incisive Coverage Tool, 其实说白了就是hdlscore。 == 验证环境 == drawing:mytest = 技术类 = |
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| drawing:mytest | [[MonthCalendar]] |
个人主页 TableOfContents 纪录一些自己经常访问的网站
个人兴趣
我是一个芯片验证工程师，在日常工作中，python是我最重要的scripting language。现在我还用python的MyHDL package来搭建testbench, it works well。我的兴趣范围还包括SystemC，SystemVerilog，testbench automation，coverage driven verification等，希望能和IC design领域的同行多多交流。
现在的项目
项目概述
建立一个嵌入式控制器芯片(SoC)的功能验证环境。这个芯片有embedded java processor，采用wishbone总线结构。
验证策略
constraint random
coverage driven
code coverage
functional coverage
assertion based
用PSL作为assertion language，并且利用其中的cover来统计control based functional coverage。
Technologies and Tools
- Simulator采用Cadence的IUS54
- Debugger采用Novas的Debussy 5.4v7。
- Code Coverage analysis采用Cadence的Incisive Coverage Tool, 其实说白了就是hdlscore。
验证环境
drawing:mytest
技术类
[http://www.python.org python官方网站]
[http://www.systemc.org OSCI官方网站]
[http://www.51eda.com/bbs 51EDA]
[http://shera-ccserver/vqwiki/jsp/index.jsp wiki in java]
[wiki:ChunLinZhang/bookmark 我经常访问的地方]
from myhdl import *
{zh} [email protected] 