|
⇤ ← Revision 1 as of 2005-06-06 15:37:02
Size: 119
Comment:
|
Size: 199
Comment:
|
| Deletions are marked like this. | Additions are marked like this. |
| Line 1: | Line 1: |
| [http://www.eetimes.com/news/design/columns/eda/showArticle.jhtml?articleID=26806455 Is SystemVerilog the next PL/1?] | * [http://www.eetimes.com/news/design/columns/eda/showArticle.jhtml?articleID=26806455 Is SystemVerilog the next PL/1?] * [http://www.deepchip.com/items/0446-06.html SystemVerilog Real Project?] |
[http://www.eetimes.com/news/design/columns/eda/showArticle.jhtml?articleID=26806455 Is SystemVerilog the next PL/1?]
[http://www.deepchip.com/items/0446-06.html SystemVerilog Real Project?]
